The present invention relates to the manufacture of electronic devices. More particularly, the invention provides a technique including a method and device for planarizing a film of material of an article such as a semiconductor wafer. However, it will be recognized that the invention has a wider range of applicability; it can also be applied to flat panel displays, hard disks, raw wafers, and other objects that require a high degree of planarity.
The fabrication of integrated circuit devices often begins by producing semiconductor wafers cut from an ingot of single crystal silicon which is formed by pulling a seed from a silicon melt rotating in a crucible. The ingot is then sliced into individual wafers using a diamond cutting blade. Following the cutting operation, at least one surface (process surface) of the wafer is polished to a relatively flat, scratch-free surface. The polished surface area of the wafer is first subdivided into a plurality of die locations at which integrated circuits (IC) are subsequently formed. A series of wafer masking and processing steps are used to fabricate each IC. Thereafter, the individual dice are cut or scribed from the wafer and individually packaged and tested to complete the device manufacture process.
During IC manufacturing, the various masking and processing steps typically result in the formation of topographical irregularities on the wafer surface. For example, topographical surface irregularities are created after metallization, which includes a sequence of blanketing the wafer surface with a conductive metal layer and then etching away unwanted portions of the blanket metal layer to form a metallization interconnect pattern on each IC. This problem is exacerbated by the use of multilevel interconnects.
A common surface irregularity in a semiconductor wafer is known as a step. A step is the resulting height differential between the metal interconnect and the wafer surface where the metal has been removed. A typical VLSI chip on which a first metallization layer has been defined may contain several million steps, and the whole wafer may contain several hundred ICs.
Consequently, maintaining wafer surface planarity during fabrication is important. Photolithographic processes are typically pushed close to the limit of resolution in order to create maximum circuit density. Typical device geometries call for line widths on the order of 0.5 xcexcM. Since these geometries are photolithographically produced, it is important that the wafer surface be highly planar in order to accurately focus the illumination radiation at a single plane of focus to achieve precise imaging over the entire surface of the wafer. A wafer surface that is not sufficiently planar, will result in structures that are poorly defined, with the circuits either being nonfunctional or, at best, exhibiting less than optimum performance. To alleviate these problems, the wafer is xe2x80x9cplanarizedxe2x80x9d at various points in the process to minimize non-planar topography and its adverse effects. As additional levels are added to multilevel-interconnection schemes and circuit features are scaled to submicron dimensions, the required degree of planarization increases. As circuit dimensions are reduced, interconnect levels must be globally planarized to produce a reliable, high density device. Planarization can be implemented in either the conductor or the dielectric layers.
In order to achieve the degree of planarity required to produce high density integrated circuits, chemical-mechanical planarization processes (xe2x80x9cCMPxe2x80x9d) are being employed with increasing frequency. A conventional rotational CMP apparatus includes a wafer carrier for holding a semiconductor wafer. A soft, resilient pad is typically placed between the wafer carrier and the wafer, and the wafer is generally held against the resilient pad by a partial vacuum. The wafer carrier is designed to be continuously rotated by a drive motor. In addition, the wafer carrier typically is also designed for transverse movement. The rotational and transverse movement is intended to reduce variability in material removal rates over the surface of the wafer. The apparatus further includes a rotating platen on which is mounted a polishing pad. The platen is relatively large in comparison to the wafer, so that during the CMP process, the wafer may be moved across the surface of the polishing pad by the wafer carrier. A polishing slurry containing chemically-reactive solution, in which are suspended abrasive particles, is deposited through a supply tube onto the surface of the polishing pad.
CMP is advantageous because it can be performed in one step, in contrast to past planarization techniques which are complex, involving multiple steps. Moreover, CMP has been demonstrated to maintain high material removal rates of high surface features and low removal rates of low surface features, thus allowing for uniform planarization. CMP can also be used to remove different layers of material and various surface defects. CMP thus can improve the quality and reliability of the ICs formed on the wafer.
Chemical-mechanical polishing is a well developed planarization technique. The underlying chemistry and physics of the method is understood. However, it is commonly accepted that it still remains very difficult to obtain smooth results near the center of the wafer. The result is a planarized wafer whose center region may or may not be suitable for subsequent processing. Sometimes, therefore, it is not possible to fully utilize the entire surface of the wafer. This reduces yield and subsequently increases the per-chip manufacturing cost. Ultimately, the consumer suffers from higher prices.
It is therefore desirable to maximize the useful surface of a semiconductor wafer to increase chip yield. What is needed is an improvement of the CMP technique to improve the degree of global planarity that can be achieved using CMP.
According to the present invention, a technique for improving chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) is provided. In an exemplary embodiment, the invention provides a polishing method for providing uniform removal of material from the surface of a substrate.
In accordance with the invention, a method for polishing semiconductor wafers includes selecting a pad offset distance and positioning a polishing pad relative to a wafer on the basis of the pad offset distance. The wafer is then polished by contacting the pad against the wafer and translating the pad across the wafer surface. The pad is translated along a curvlinear path defined by the traversal of the pad axis. The path has a minimum separation distance from the axis of rotation of the wafer substantially equal to the offset distance. The path can be arbitrary, so long as the offset distance is not violated. In a particular embodiment of the invention, the path follows a linear path parallel to a line through the center of the wafer; the linear path being separated from the centerline by the offset distance. During the polish operation, the translational velocity of the pad is varied in accordance with a velocity profile corresponding to the selected offset distance. The wafer and the pad each is rotated in a direction opposite the other.
Further in accordance with the invention, the pad offset distance is determined by selecting a first offset distance. The pad is positioned relative to a test wafer based on this first offset distance. A polish of the test wafer is performed. The pad is translated at a constant velocity across the wafer. A removal profile of the resulting polished test wafer is then produced. Based on the characteristics of the removal profile, a second offset distance is selected and the process is repeated on a second test wafer. The subsequent pad offset distance may be greater than or less than the previous offset distance. When the desired removal profile is achieved, the corresponding offset distance is stored. A velocity profile is then generated based on the shape of the removal profile. Thus, in a subsequent polish of a production wafer, the polishing pad is positioned based on the offset distance and translated across the wafer in accordance with the velocity profile to produce a high quality polish exhibiting global uniform planarity of the wafer surface.
The present invention achieves these benefits in the context of known process technology and known techniques in the mechanical arts. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.